Cisco Systems India Freshers Off Campus Event - Registration Opens | Role: Hardware Engineer | Date: Feb 2016 @ Bangalore

Cisco Systems India Freshers Off Campus Event - Registration Opens | Role: Hardware Engineer | Date: Feb 2016 @ Bangalore

About Company : 






Cisco Services Technology Group (CSTG), are searching for Software Engineer to be a fundamental piece of our group in conveying an exceedingly quality, solid, and powerful applications for our association. As an individual from the designing group, one is required to create, investigate, and ace the present device improvements furthermore supporting the same amid use. As a very specialized inventive individual you will work intimately with different designers, specialized leads and draftsmen on configuration and execution of in-house

frameworks and execution testing.

Organization Name Cisco

Organization Website www.cisco.com

Experience 0-1 Years

Salary Not Mentioned

Qualification B.E/B.Tech/M.E/M.Tech

Skills C, and C++

Work Role Hardware Engineer

Work Location Bangalore

Work Type Apply

Last date to apply Feb 2016

Reference Latestbowl.in

Portrayal : 
  • Chosen applicants will partake in the configuration and confirmation process beginning with abnormal state calculated and compositional examinations and closure with smaller scale structural planning and outline segment inside of the ASIC. 
  • Chosen hopefuls will find that outline courses, for example, computerized rationale, PC structural engineering and association, and system/correspondence building design will be exceptionally useful all through this stage. 
  • Datapath pipelines, state-machines, and PC number juggling components are key segments inside of the ASIC. 
Qualification:
  • B.E/B.Tech/M.E/M.Tech from perceived college 
  • Equipment outline, the test/check environment is planned utilizing an article situated system composed in C++ so you will utilize information from your programming courses that incorporate development information structures, calculations, and configuration designs and also dialects, for example, Verilog HDL, C, and C++. 
  • You will help in the structural engineering of the test situations which incorporate creating obliged irregular boost generators, computerized reaction checkers, and propelled arrangement and programming API segments. 
  • Some of these segments are reused over the whole period of the venture from module, chip and framework level check on Linux based verilog test systems. 
  • Critical thinking aptitudes and out-of-the-crate deduction to make zone and power effective equipment outlines and additionally reusable C++ classes for the check and reproduction situations. 
  • Composing intensive and nitty gritty details and test arranges and in addition oral portrayals will empower your thoughts and ideas to be explored and acknowledged by other colleagues.
Cisco Registration Link And Freshers Info:

                           Link-2



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